ISBN-10: 0738158003
ISBN-13: 9780738158006
Summary: VHSIC Description Language (VHDL) is outlined. VHDL is a proper notation meant to be used in all levels of the construction of digital platforms. since it is either desktop readable and human readable, it helps the improvement, verification, synthesis, and trying out of designs; the conversation of layout information; and the upkeep, amendment, and procurement of undefined. Its fundamental audiences are the implementors of instruments aiding the language and the complicated clients of the language.
Keywords: computing device languages, digital platforms, undefined, layout, VHDL
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Extra info for 1076-2008 IEEE Standard VHDL. Language Reference Manual
Example text
Package_declaration ::= package identifier is package_header package_declarative_part end [ package ] [ package_simple_name ] ; package_header ::= [ generic_clause [ generic_map_aspect ; ] ] package_declarative_part ::= { package_declarative_item } package_declarative_item ::= subprogram_declaration | subprogram_instantiation_declaration | package_declaration | package_instantiation_declaration | type_declaration | subtype_declaration | constant_declaration | signal_declaration | variable_declaration | file_declaration | alias_declaration | component_declaration | attribute_declaration | attribute_specification | disconnection_specification | use_clause | group_template_declaration | group_declaration | PSL_Property_Declaration | PSL_Sequence_Declaration If a simple name appears at the end of the package declaration, it shall repeat the identifier of the package declaration.
Restrictions apply. IEEE STANDARD VHDL LANGUAGE REFERENCE MANUAL IEEE Std 1076-2008 A given subprogram designator can be used to designate multiple subprograms. The subprogram designator is then said to be overloaded; the designated subprograms are also said to be overloaded and to overload each other. If two subprograms overload each other, one of them can hide the other only if both subprograms have the same parameter and result type profile. A call to an overloaded subprogram is ambiguous (and therefore is an error) if the name of the subprogram, the number of parameter associations, the types and order of the actual parameters, the names of the formal parameters (if named associations are used), and the result type (for functions) are not sufficient to identify exactly one (overloaded) subprogram.
All rights reserved. com 免费下载 Authorized licensed use limited to: Queen Mary University of London. Downloaded on March 1, 2009 at 21:16 from IEEE Xplore. Restrictions apply. 10 Conformance rules Whenever the language rules either require or allow the specification of a given subprogram to be provided in more than one place, the following variations are allowed at each place: — A numeric literal can be replaced by a different numeric literal if and only if both have the same value. — A simple name can be replaced by an expanded name in which this simple name is the suffix if, and only if, at both places the meaning of the simple name is given by the same declaration.
1076-2008 IEEE Standard VHDL. Language Reference Manual
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